1. Technical Field
The present disclosure relates to a semiconductor device and a method of manufacturing the same.
2. Related Art
In order to keep up with demands on portable information devices or small electronic appliances, such as high performance and miniaturization, high-density mounting technologies of semiconductor device are currently under research and development. Among these technologies, Wafer Level Packaging (WLP) technology, which fabricates packages while maintaining the size of semiconductor wafers, is regarded as having an important role. A new package is provided as a Chip Size Package (CSP), which is divided in a respective semiconductor chip package. The CSP, in the form of a single or additionally-coupled unit, is assembled to or mounted inside an application device. In response to recent advancements in content technologies and demands on the increasingly large capacity of memory, chip-mounting technologies in one field of the CSP have been widely used. The chip-mounting technologies are technologies for assembling semiconductor chips of known reliability on a new package by stacking the semiconductor chips one on another (see e.g., JP-A-2000-340694 and Japanese Patent No. 3895768).
JP-A-2000-340694 discloses chip-stacking technology and, more particularly, discloses one type of a semiconductor chip stack, which requires a complicated fabrication process when connecting from outside to the side surfaces of the semiconductor chips after the dicing of a wafer. For example, this is a complicated process using an anisotropic conductive film or a flexible circuit substrate or forming an insulating film and a conductive film after stacking multiple layers of semiconductor chips. In addition, Japanese Patent No. 3895768 discloses another type of a semiconductor chip stack as shown in FIG. 1, and requires a complicated process, which includes, for example, sputtering nitrides to insulate the side surfaces 12 of semiconductor chips 11 after dicing the semiconductor chips. As above, the fabrication process including the stacking of chips is complicated and has an adverse effect on the quality of products.